1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor memory device, such as a flash memory, etc, and write-in method thereof.
2. Description of the Prior Art
For a NAND type non-volatile semiconductor memory device, a plurality of memory cell transistors (or so-called memory cells hereinafter) are series connected between bit lines and source lines, forming a NAND string. Such NAND type non-volatile semiconductor memory devices are highly integrated and are well known for those skilled in the art (see non-patent documents 1-4).
For common NAND type non-volatile semiconductor memory devices, when an erasing operation is performed, a high voltage, for example, 20V, is applied to a semiconductor substrate thereof and no voltage, for example, 0V, is applied to a word line thereof. Electrons may be removed from a floating gate, a charge storage layer formed of poly-silicon material, such that a threshold voltage becomes lower than an erasing threshold value, for example, −3V. Meanwhile, when a write-in (programming) operation is performed, no voltage, for example, 0V, is applied to a semiconductor substrate thereof and a high voltage, for example 20V, is applied to a controlling gate thereof. Following, electrons are injected from the semiconductor substrate to the floating gate, such that the threshold voltage becomes higher than a write-in threshold voltage, for example, 1V. A state of such a memory cell is determined by identifying a current therethrough, wherein a read-out voltage, for example, 0V, between the write-in threshold voltage and the read-out threshold voltage is applied to the control gate.
For the described non-volatile semiconductor memory device, when a programming operation, such as a write-in operation, is performed to the memory cell which is a write-in target, electrical charges are injected into the floating gate of the memory cell transistor and the threshold voltage rises. Therefore, the state of writing-in data “0” may be achieved, even if a below threshold voltage is applied to the gate, as no current would flow. Commonly, a threshold voltage of a memory cell on an erasing state is not uniform. Therefore, if a determined write-in voltage is applied to carry out a programming operation and threshold voltages are verified that they are higher than a verify-level, the threshold voltages of the memory cell after the write-in operation will have a distribution above the verify-level.
A non-volatile semiconductor memory device including multi-valued memory cells provides multi-values by setting different threshold voltages to the memory cells. In the case of a non-volatile semiconductor memory device, if threshold voltages are widely distributed, the interval between adjacent level voltage values will become narrow, such that it becomes difficult to faithfully store data. To solve this problem, patent document 5 discloses a non-volatile memory core circuit, which stores multi-values by setting a plurality of different threshold voltages to the memory cells. Also a control circuit is disclosed, which controls write-in operations of the memory core circuit. When memory cells are to be programmed to one threshold voltage, the control circuit programs memory cells set at that one threshold voltage and other memory cells set at a threshold voltage which is higher than that one threshold voltage, to that one threshold voltage. The control circuit programs the memory cells from the lowest threshold voltage among the plurality of different voltages to the highest threshold voltage.
Patent document 1 JP H09-147582;
Patent document 2 JP 2000-285692;
Patent document 3 JP 2003-346485;
Patent document 4 JP 2001-028575;
Patent document 5 JP 2001-325796;
Patent document 6 JP 2006-099912;
Patent document 7 JP 2004-326866; and
Patent document 8 JP 2007-207332.
However, in a multi-valued non-volatile semiconductor memory device, when a write-in operation of a memory cell is completed by using a bit line and a word line adjacent to the bit line, the threshold voltage distribution of the memory cell surrounded by the bit line and the word line will rise (this phenomenon is called the “rising threshold voltage distribution”, hereafter). As disclosed in Patent document 7, the phenomenon is caused by the capacitive coupling interference effect between the floating gates of memory cells which are contiguous to each other. Also, in the case of a write-in operation of a floating gate of an adjacent memory cell (which means that electrons are injected into a floating gate), the voltage level of the floating gate of a targeted memory cell is drawn down (which means that the threshold voltage rises). The situation is shown in FIG. 5, wherein FIG. 5(a) shows the data of the target memory cell before/after the write-in operation of the adjacent memory cell and FIG. 5(b) shows a write-in operation of an adjacent memory cell which is performed by the write-in method of FIG. 4.
FIG. 4-FIG. 7 show possibility distributions of threshold voltages (Vt distribution) of a 4-valued flash EEPROM based on the write-in method of the prior art and embodiments of the invention. The write-in operation of a 2-bits multi level cell is divided into write-in of the lowest bit (LSB) and write-in of the highest bit (MSB), as shown in FIG. 4(a) and FIG. 4(b), respectively. The reason is the fact that rising threshold voltage distribution which is caused by the shifting of the threshold voltage (Vth) during the LSB write-in operation can be cancelled during the MSB write-in operation. The details are recorded in patent document 8. Here, as shown in FIG. 4, the degree of change for the threshold voltage (Vth) during the MSB write-in operation from the data (1, 1) to the data (0, 1) ΔVth2 is twice as much as that of the degree of change for the threshold voltage (Vth) during the MSB write-in operation from the LSB data (1, 0) to the data (0, 0) ΔVth1. Therefore, the rising phenomenon of the threshold voltage is great. As shown in FIG. 6, to perform a weak write-in operation (soft programming) after data cancelled so as to narrow the distribution width of the threshold voltage after cancellation is attempted.
A soft programming operation of the prior art, is executed within all memory cells and a verifying operation is proceed by all word lines, such that narrowing the distribution of the threshold voltage is limited. If the distribution (1, 1) is able to be narrowed to the distribution shown by oblique lines in FIG. 7, the effect of the threshold voltage may be reduced greatly.
The purpose of this invention is to provide a non-volatile semiconductor memory device and write-in method thereof, which solves the above problems, wherein when a write-in operation of a memory cell is completed by using a bit line and a word line adjacent to the bit line, a rising phenomenon of a threshold voltage of a memory cell surrounded by the bit line and the word line is minimized.